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Today's base band system on a chip (SoC) has multiple homogenous and heterogeneous digital signal processor (DSP)/central processing unit (CPU) elements, hardware accelerators etc. (collectively “processing elements”) accessing the same memory blocks, versus the tradition architectures where a single DSP/CPU processing element manages the entire resources on chip. In prior devices, one DSP/CPU element owned all the resources and accessed them with physical addressing. Low power management for the memory resources was managed and initiated by the DSP/CPU element. Static and explicit memory organization was done by the DSP/CPU element. Memory resources behaved like a dummy slave without any intelligence in terms of power and memory resources management.
This methodology become more and more cumbersome for a multiple processing element scenario since each processing element allocates and accesses the shared resources independently, making power management effectively a game theory problem.